A device of etching the semiconductor in plasma has been known as a means of treating the semiconductor surface. The following describes the prior art with reference to a device based on the ECR (electron cyclotron resonance) method. This is the method to generate plasma through microwaves in a vacuum container where magnetic field is applied from outside. The magnetic field causes electron to perform cyclotron movement, and this frequency and that of the microwaves are made to resonate with each other, thereby ensuring effective generation of plasma. Radio frequency voltage is applied to the sample in order to accelerate ion incident upon a sample such as a semiconductor device. Halogen gas such as chlorine and fluorine is used as a gas to become plasma.
Such a conventional device is disclosed in Japanese Patent Laid-Open No. 151360/1994 (corresponding Specifications of U.S. Pat. No. 5,352,324) mainly to increase the processing accuracy. According to this invention, selectivity between silicon (Si) as a substance to be etched and substrate oxide film is increased and dependency on aspect ratio is reduced by intermittent on/off control of the radio frequency voltage applied to the sample. Japanese Patent Laid-Open No. 339989/1996 (corresponding Specifications of U.S. Pat. No. 5,614,060) discloses that etching residues can be reduced in metal etching by superimposition of short pulses of intermittent RF bias power. Japanese Patent Laid-open No. 154734/1987 shows a method of processing inclined portions, wherein d.c. bias higher than the specified potential and lower d.c. bias than that are applied alternately by introduction of gas causing deposition and etching.
Japanese Patent Laid-open No. 50923/1985 (corresponding Specifications of U.S. Pat. No. 4,579,623) discloses a method of improving the surface treatment characteristics by periodic change of the volume of etching gas to be introduced and change of radio frequency voltage application time. Furthermore, Japanese Official Gazette No. 69415/1992 (corresponding Specifications of U.S. Pat. No. 4,808,258) discloses a method of improving etching characteristics by changing the radio frequency voltage applied to the sample. Still further, U.S. Pat. No. 4,585,516 discusses a method of improving a uniform etching rate inside the wafer surface by changing the radio frequency voltage of at least one of the radio frequency power supplies connected to two of three electrodes in a three-electrode etching device. Conductive portions of the electrode and wiring of the LSI (Large Scale Integrated circuit) are required to have a lower resistance by higher speed and lower power consumption in recent years. One of the solutions to meet this requirement is a way of using tungsten and other metals to form the gate electrode of the MOS (Metal Oxide Semiconductor) device which where polycrystalline silicon has been used conventionally. Since the current technology is not sufficient to form metallic film directly on the oxide film, this method provides a way of forming polycrystalline silicon film on the oxide film, and forming and metal film thereon. This method is attracting attention as one of the most promising methods. Furthermore, a barrier film such as titanium nitride is required to minimize diffusion between the polycrystalline silicon film and metallic film. Without barrier film, polycrystalline silicon and metal will be mixed by dispersion due to heating process after film formation, resulting in higher resistance.
Etching of the film with multilayer architecture as discussed above raises new problems which are caused by etching reaction between the polycrystalline silicon and metal. For example, the optimum values are different between the metal and polycrystalline silicon, so sample temperature is set at an intermediate value. Then metal or barrier film remain unevenly on the polycrystalline silicon, causing irregularities on the etching surface. Higher speed and lower power consumption in recent years require CMOS (Complementary Metal Oxide Semiconductor) to be produced in a dual gate architecture where polycrystalline silicon as a gate electrode on the pMOS side is doped into a p-architecture, and that on the nMOS side is doped in a n-type.
Etching of the film with gate electrodes having different conductivities involves unprecedented issues. For example, increase in the number of photolithographic processes to perform independent etching of p-type and n-type gates will result in higher production costs. This will require simultaneous etching of both p- and n-type gates. However, simultaneous etching of both p- and n-type gates will cause earlier exposure of the underlying gate oxide film on the n-type side since the etching rate of the n-type polycrystalline silicon is higher; this will result in a thinner oxide film on the n-type side or separation of oxide film on the n-type side. Besides, side etching is more likely to occur in the n-type gate Miniaturization of semiconductor devices in recent years has come to require higher precision in processing. One of the ensuing problems to be solved relates to the mask to form very small patterns. A resist as an organic substance is mainly used as a mask material. However, the resist normally has a thickness of about 1 micron. So the resist itself provides a groove with a higher aspect ratio, resulting in more difficult processing of a narrow groove. If the resist is made thinner, it will be no further resist left before underling processing completes. Solution to this problem is provided by the method of using as mask material an inorganic substance including oxide film called a hard mask. The oxide film has five times as durable as the resist, and allows its thickness to be reduced to one fifth or more. This increases the selectivity of the etched material and mask over that when the resist is used; this is a substantial improvement. However, processing of a very thin hard mask involves a new problem of requesting further improvement of the selectivity between the underlying substance as an etched material and hard mask.
Meanwhile, processing dimensions for the line and space corresponding to wiring and electrodes are placed on the level of 1 micron or less, or preferably 0.5 micron or less as a result of miniaturization of semiconductor devices. In the processing of such minute patterns, the line is gradually increased in thickness and the pattern cannot be designed to have the design dimensions. This will create a serious issue. Furthermore, in addition to the differences of etching rate inside the minute groove and on the wider portion, differences in shape, so-called microloading will present a serious issue, which will cause processing failure.
Furthermore, the oxide film of said MOS transistor gate is 6 nm thick or less in the memory device of 256M or thereafter. In such a device, a trade-off relationship is established in selectivity between an isotropy and underlying oxide film, and this makes processing more difficult. Many of said prior arts were invented when the minimum processing dimensions of the element is 1 micron or more. These inventions are finding it difficult to cope with processing of more minute elements. Processing of such minute elements requires assembling under compact process conditions based on analysis of the relationship between the physical volume of plasma and etching characteristics, and many manufacturers are currently spending a lot of time and labor in this direction. The constructed process permits new devices of different quality to be processed.